Logic synthesis and verification algorithms (Book, 2006) [Portland Community College Library]
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Logic synthesis and verification algorithms

Author: Gary D Hachtel; Fabio Somenzi
Publisher: New York : Springer, ©2006.
Edition/Format:   Print book : English : 1st softcover edView all editions and formats
Summary:

This book blends mathematical foundations and algorithmic developments with circuit design issues. Through the study of optimal two-level and multilevel combinational circuit design, the reader is  Read more...

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Details

Material Type: Internet resource
Document Type: Book, Internet Resource
All Authors / Contributors: Gary D Hachtel; Fabio Somenzi
ISBN: 9780387310046 0387310045 0306475928 9780306475924 0387310053 9780387310053 8181284836 9788181284839
OCLC Number: 68629693
Description: xxxii, 564 pages : illustrations ; 26 cm
Contents: I: Introduction.1. Introduction.2. A Quick Tour of Logic Synthesis with the Help of a Simple Example.- II: Two Level Logic Synthesis. 3. Boolean Algebras. 4. Synthesis of Two-Level Circuits. 5. Heuristic Minimization of Two-Level Circuits. 6. Binary Decision Diagrams (BDDs).- III: Models of Sequential Systems. 7. Models of Sequential Systems. 8. Synthesis and Verification of Finite State Machines. 9. Finite Automata. IV: Multilevel Logic Synthesis. 10. Multi-Level Logic Synthesis. 11. Multi-Level Minimization. 12. Automatic Test Generation for Combinational Circuits. 13. Technology Mapping. A. ASCII Codes. B. Supplementary Problems.- Bibliography.- Index.
Responsibility: Gary Hachtel, Fabio Somenzi.
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