Electronic design automation : synthesis, verification, and test (eBook, 2009) [Portland Community College Library]
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Electronic design automation : synthesis, verification, and test

Author: Laung-Terng Wang; Yao-Wen Chang; Kwang-Ting Cheng
Publisher: Burlington, MA : Morgan Kaufmann Publishers/Elsevier, 2009.
Edition/Format:   eBook : Document : EnglishView all editions and formats
Summary:
This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms,  Read more...
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Details

Material Type: Document, Internet resource
Document Type: Internet Resource, Computer File
All Authors / Contributors: Laung-Terng Wang; Yao-Wen Chang; Kwang-Ting Cheng
ISBN: 9780123743640 0123743648
OCLC Number: 964711262
Notes: Ch. 14. Fault Simulation and Test Generation / James C.-M. Li and Michael S. Hsiao.
Description: 1 online resource
Contents: Ch. 1. Introduction / Charles E. Stroud, Lang-Terng Wang and Yao-Wen Chang --
Ch. 2. Fundamentals of CMOS design / Xinghao Chen and Nur A. Touba --
Ch. 3. Design for testability / Laung-Terng Wang --
Ch. 4. Fundamentals of algorithms / Chung-Yang Huang, Chao-Yue Lai and Kwang-Ting Cheng --
Ch. 5. Electronic system-level design and high-level synthesis / Jianwen Zhu and Nikil Dutt --
Ch. 6. Logic synthesis in a nutshell / Jie-Hong Jiang and Srinivas Devadas --
Ch. 7. Test synthesis / Laung-Terng Wang, Xiaoqing Wen and Shianling Wu --
Ch. 8. Logic and circuit simulation / Jiun-Lang Huang, Cheng-Kok Koh and Stephen F. Cauley --
Ch. 9. Functional verification / Hung-Pin Wen, Li-C. Wang and Kwang-Ting Cheng --
Ch. 10. Floorplanning / Tung-Chieh Chen and Yao-Wen Chang --
Ch. 11. Placement / Chris Chu --
Ch. 12. Global and detailed routing / Huang-Yu Chen and Yao-Wen Chang --
Ch. 13. Synthesis of clock ad power/ground networks / Cheng-Kok Koh, Jitesh Jain and Stephen F. Cauley.
Responsibility: edited by Laung-Terng Wang, Yao-Wen Chang, Kwang-Ting (Tim) Cheng.

Abstract:

This book provides broad and comprehensive coverage of the entire EDA flow. EDA/VLSI practitioners and researchers in need of fluency in an "adjacent" field will find this an invaluable reference to the basic EDA concepts, principles, data structures, algorithms, and architectures for the design, verification, and test of VLSI circuits. Anyone who needs to learn the concepts, principles, data structures, algorithms, and architectures of the EDA flow will benefit from this book. Covers complete spectrum of the EDA flow, from ESL design modeling to logic/test synthesis, verification, physical design, and test - helps EDA newcomers to get "up-and-running" quickly Includes℗ comprehensive coverage of EDA concepts, principles, data structures, algorithms, and architectures - helps all readers improve their VLSI design competence Contains latest advancements not yet available in other books, including Test compression, ESL design modeling, large-scale floorplanning, placement, routing, synthesis of clock and power/ground networks - helps readers to design/develop testable chips or products Includes industry best-practices wherever appropriate in most chapters - helps readers avoid costly mistakes.
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